--quartus 2 编写 输出为数码管 直接编译就可以 FPGA library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lift is
port (floor_1_up,floor_2_up,floor_2_down,floor_3_down:in std_logic; floor1,floor2,floor3:in std_logic;
clk:in std_logic;
floor_num:out std_logic_vector(6 downto 0);
direct:out std_logic_vector(6 downto 0);
open_close: out std_logic);
end;
architecture bev_lift of lift is
signal up:std_logic_vector(3 downto 1);
signal down:std_logic_vector(3 downto 1);
signal now_num:integer range 1 to 3;
signal flag:integer range 0 to 1;
signal run:integer range 0 to 1;
signal show_direct:integer;
signal OC:integer;
signal up_c:std_logic_vector(3 downto 1);
signal down_c:std_logic_vector(3 downto 1);
begin
control:process(floor_1_up,floor_2_up,floor_2_down,floor_3_down,clk, floor1,floor2,floor3)
variable up_v:std_logic_vector(3 downto 1):="000"; variable down_v:std_logic_vector(3 downto 1):="000"; begin
if(clk'event and clk='1') then
up_v:="000";
down_v:="000";
if(floor_1_up='1') then
up_v(1):='1';end if;
if(floor_2_up='1') then
up_v(2):='1';end if;
if(floor_2_down='1') then
down_v(2):='1';end if;
if(floor_3_down='1') then
down_v(3):='1';end if;
if(floor1='1') then
if(now_num>1) then
down_v(1):='1';
end if;
end if;
if(floor2='1') then
if(now_num>2) then
down_v(2):='1';end if;
if(now_num
up_v(2):='1'; end if;
end if;
if(floor3='1') then
if(now_num
up_v(3):='1';end if;
end if;
end if;
if(clk'event and clk='1') then
up_c
down_c
end if;
end process;
go:process(clk)
variable now_num_v :integer range 0 to 4:=1;
variable next_num_v :integer range 0 to 4:=1;
variable flag_v: integer range 0 to 1;
variable clear: integer range 0 to 1:=0;
variable delay:integer range 1 to 6:=1;
variable OC:integer range 0 to 1:=0;
variable first:integer range 0 to 1:=0;
variable next_num:integer range 1 to 3;
begin
if(clk'event and clk='0') then
up
down
if(flag=0) then
if(run=0) then
if(next_num_v>=1) then
if(down(next_num_v)='1') then run
next_num:=next_num_v; clear:=1;
first:=1;
else
next_num_v:=next_num_v-1; end if;
if(clear=1) then down(next_num_v)
up(next_num_v)3) then flag_v:=0; next_num_v:=3;end if; end if; end if; end if; flagnext_num) then show_direct
end if;
if(OC=1) then
open_close
delay:=delay+1;
if(delay=6) then
delay:=1;
open_close
next_num_v:=now_num; run
end if;
end if;
end if;
end process;
dir:process(show_direct)
variable n:integer range 1 to 2;
begin
case show_direct is
when 1 =>directdirect
when others =>direct
end process;
show_num:process(clk)
begin
case now_num is
when 1 =>floor_numfloor_numfloor_num
when others =>floor_num
end process;
end architecture;
--quartus 2 编写 输出为数码管 直接编译就可以 FPGA library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lift is
port (floor_1_up,floor_2_up,floor_2_down,floor_3_down:in std_logic; floor1,floor2,floor3:in std_logic;
clk:in std_logic;
floor_num:out std_logic_vector(6 downto 0);
direct:out std_logic_vector(6 downto 0);
open_close: out std_logic);
end;
architecture bev_lift of lift is
signal up:std_logic_vector(3 downto 1);
signal down:std_logic_vector(3 downto 1);
signal now_num:integer range 1 to 3;
signal flag:integer range 0 to 1;
signal run:integer range 0 to 1;
signal show_direct:integer;
signal OC:integer;
signal up_c:std_logic_vector(3 downto 1);
signal down_c:std_logic_vector(3 downto 1);
begin
control:process(floor_1_up,floor_2_up,floor_2_down,floor_3_down,clk, floor1,floor2,floor3)
variable up_v:std_logic_vector(3 downto 1):="000"; variable down_v:std_logic_vector(3 downto 1):="000"; begin
if(clk'event and clk='1') then
up_v:="000";
down_v:="000";
if(floor_1_up='1') then
up_v(1):='1';end if;
if(floor_2_up='1') then
up_v(2):='1';end if;
if(floor_2_down='1') then
down_v(2):='1';end if;
if(floor_3_down='1') then
down_v(3):='1';end if;
if(floor1='1') then
if(now_num>1) then
down_v(1):='1';
end if;
end if;
if(floor2='1') then
if(now_num>2) then
down_v(2):='1';end if;
if(now_num
up_v(2):='1'; end if;
end if;
if(floor3='1') then
if(now_num
up_v(3):='1';end if;
end if;
end if;
if(clk'event and clk='1') then
up_c
down_c
end if;
end process;
go:process(clk)
variable now_num_v :integer range 0 to 4:=1;
variable next_num_v :integer range 0 to 4:=1;
variable flag_v: integer range 0 to 1;
variable clear: integer range 0 to 1:=0;
variable delay:integer range 1 to 6:=1;
variable OC:integer range 0 to 1:=0;
variable first:integer range 0 to 1:=0;
variable next_num:integer range 1 to 3;
begin
if(clk'event and clk='0') then
up
down
if(flag=0) then
if(run=0) then
if(next_num_v>=1) then
if(down(next_num_v)='1') then run
next_num:=next_num_v; clear:=1;
first:=1;
else
next_num_v:=next_num_v-1; end if;
if(clear=1) then down(next_num_v)
up(next_num_v)3) then flag_v:=0; next_num_v:=3;end if; end if; end if; end if; flagnext_num) then show_direct
end if;
if(OC=1) then
open_close
delay:=delay+1;
if(delay=6) then
delay:=1;
open_close
next_num_v:=now_num; run
end if;
end if;
end if;
end process;
dir:process(show_direct)
variable n:integer range 1 to 2;
begin
case show_direct is
when 1 =>directdirect
when others =>direct
end process;
show_num:process(clk)
begin
case now_num is
when 1 =>floor_numfloor_numfloor_num
when others =>floor_num
end process;
end architecture;