二选一选择器_verilog

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company:

// Engineer:

// // Create Date: 2015/07/07 10:22:26

// Design Name: // Module Name: muxtwo

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

// // Revision: // Revision 0.01 - File Created // Additional Comments:

// ////////////////////////////////////////////////////////////////////////////////// module muxtwo(out,a,b,sl );

input a,b,sl;

output out;

reg out;

always @(a or b or sl)

if(! sl)

out = a;

else

out = b;

Endmodule

//testbench `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company:

// Engineer:

// // Create Date: 2015/07/07 10:30:21

// Design Name: // Module Name: muxtwo_testbench

// Project Name:

// Target Devices:

/

//

////////////////////////////////////////////////////////////////////////////////// module muxtwo_testbench(); reg a; reg b; reg sl; wire out; muxtwo uut(

.a(a),

.b(b),

.sl(sl),

.out(out) ); initial begin

while(1)

begin

a = 0;

b = 0;

sl= 0;

#100;

a = 1;

b = 0;

sl= 0;

#100;

a = 0;

b = 0;

sl= 1;

#100;

a = 0;

b = 1;

sl= 1;

#100;

a = 1;

b = 1;

sl= 1;

#100;

end

$display("Verilog muxtwo test!=%d",out); end

endmodule

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company:

// Engineer:

// // Create Date: 2015/07/07 10:22:26

// Design Name: // Module Name: muxtwo

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

// // Revision: // Revision 0.01 - File Created // Additional Comments:

// ////////////////////////////////////////////////////////////////////////////////// module muxtwo(out,a,b,sl );

input a,b,sl;

output out;

reg out;

always @(a or b or sl)

if(! sl)

out = a;

else

out = b;

Endmodule

//testbench `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company:

// Engineer:

// // Create Date: 2015/07/07 10:30:21

// Design Name: // Module Name: muxtwo_testbench

// Project Name:

// Target Devices:

/

//

////////////////////////////////////////////////////////////////////////////////// module muxtwo_testbench(); reg a; reg b; reg sl; wire out; muxtwo uut(

.a(a),

.b(b),

.sl(sl),

.out(out) ); initial begin

while(1)

begin

a = 0;

b = 0;

sl= 0;

#100;

a = 1;

b = 0;

sl= 0;

#100;

a = 0;

b = 0;

sl= 1;

#100;

a = 0;

b = 1;

sl= 1;

#100;

a = 1;

b = 1;

sl= 1;

#100;

end

$display("Verilog muxtwo test!=%d",out); end

endmodule